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1. Field of the Invention
The invention relates generally to the field of semiconductor chip packaging. More particularly, the invention relates to the joining of the semi-conductor chip and a substrate using a flip chip process.
2. Description of the Related Art
Traditionally, semi-conductor chips have been electrically coupled to electrical traces on a substrate via wire interconnects that are soldered on one end to the top area of a chip and soldered to trace pads on the substrate that surround the chip on the other end. These types of interconnects are not particularly space efficient, requiring area for both the footprint of the chip and a trace pad perimeter. To more efficiently utilize the substrate surface and facilitate smaller chip packages, the flip chip interconnection process was developed. Essentially, the active surface of the semi-conductor chip is flipped over to face the substrate and the chip is soldered directly to trace pads located adjacent to the active surface. The result is a more compact and space efficient package.
One of the most successful and effective methods of electrically connecting a flipped chip to a substrate utilizes controlled-collapse chip connection technology (the C4 process developed by Intel Corporation of Santa Clara Calif.). Details of this process will be described below with reference to FIG. 1. Briefly, the process consists of applying solder bumps to pads on the substrate. A flux is applied to at least one of the surfaces to be joined to isolate the surface from the atmosphere and provide an adhesive force to hold the chip to the substrate during the process. The solder is then re-flowed, finally, a wash and bake cycle may be used to clean the package.
An epoxy under-fill is applied between the active surface of the chip and the top surface of the substrate to surround and support the solder interconnects. Under-filling significantly increases the reliability and fatigue resistance of the package""s interconnections. The under-fill helps to more evenly distribute stress caused by thermally induced strains due to the differences in coefficients of thermal expansion (CTE) between the chip and substrate across the entire surface of the chip and substrate. If the gap between the interconnected chip and substrate were not under-filled, the stress would be carried by the relatively thin solder interconnects, often resulting in premature package failure. However, in order for the under-fill to perform properly, it must be well adhered to the chip and substrate surfaces. Even a thin film of flux residue can cause premature delamination of a bonded surface, eventually resulting in failure in one or more of the interconnects. Accordingly, one of the great challenges using C4 technology has been to completely remove all flux residues from the package. This has become especially troublesome as the thickness of the gap between the chip and the substrate has decreased.
The total throughput time (TPT), or the time it takes to create a soldered chip, is affected significantly by the time required to remove absorbed water from chip and substrate which can be particularly time-consuming. For instance, chemical defluxing may take minutes, while a post-bake to remove absorbed water from chip and substrate may take several hours. Fluxes have been developed that completely volatilize at elevated temperature. However, because the flux is required in the C4 process to hold the chip and substrate together before re-flow, only those fluxes that have volatilization temperature at or above the solder melting point are suitable for use with the C4 process. The small thickness of the gap distance between the chip and the substrate coupled with the flux""s high volatilization temperatures, however, make it difficult, if not impossible, to boil off all of the flux residues during the re-flow process or in a subsequent post-bake operation at a temperature slightly below solder melting temperature. The long post-bake times and defluxing operations required to volatize the flux eliminate any opportunity for significant TPT reductions.